Dr. Kazuo Yano
Hitachi Ltd., Japan
Kazuo Yano received the B. S., M. S., and Ph. D degrees from Waseda University, Japan, in 1982, 1984, 1993, respectively. From 1991 to 1992 he was a Visiting Scientist at the Arizona State University.
Since he joined Hitachi Ltd. in 1984, he has explored the fusion of technology layers. He has conceived the complementary pass-transistor logic (CPL), which is known to be one of the best energy-efficient logic families, and has also done pioneering work on world-first room-temperature single-electron memories. He supervised research teams of SuperH mobile application processors, which are used for camera phones worldwide. He has expanded activities to life and business microscope, sensor-net, and advanced human interaction. Since 2006, he is a Senior Chief Researcher and the Director of the Human Information Laboratory. He is a Fellow of the IEEE, a member of the Japan Society of Applied Physics, and the IEICE of Japan. He served on Technical Program Committee Members of IEDM, DAC, ASSCC and ASP-DAC, and is serving on TPC of SPOTS and EmNet. He is the Symposium Co-Chairman/Chairman of 2008/2009 Symposium on VLSI Circuits. He received 1994 IEEE Paul Rappaport Award, 1996 IEEE Lewis Winner Award and 1998 IEEE Jack Raper Award, Most Promising Scientists Award of 2007 Ettore Majorana International School on Mind, Brain, and Education